Nonvolatile memory cells that are electrically programmable and erasable can be realized as charge-trapping memory cells, which comprise a memory layer sequence of dielectric materials with a memory layer between confinement layers of dielectric material having a larger energy band gap than the memory layer. The memory layer sequence is arranged between a channel region within a semiconductor body and a gate electrode provided to control the channel by means of an applied electric voltage. Charge carriers moving from source to a drain through the channel region are accelerated and gain enough energy to be able to penetrate the lower confinement layer and to be trapped within the memory layer. Alternatively, the application of a high gate voltage enables charge carriers to tunnel through the lower confinement layer and to be trapped in the memory layer. The trapped charge carriers change the threshold voltage of the cell transistor structure. Different programming states can be read by applying the appropriate reading voltages. Examples of charge-trapping memory cells are the SONOS memory cells, in which each confinement layer is an oxide and the memory layer is a nitride of the semiconductor material, usually silicon.
Typical applications of memory products require a steady miniaturization of the memory cells. A reduction of the area that is required by an individual memory cell can be obtained by shrinking the cell structure or by an increase of the number of bits that can be stored within one memory cell transistor structure.
In the publication of Suk-Kang Sung et al.: “Fabrication and Program/Erase Characteristics of 30-nm SONOS Nonvolatile Memory Devices” in IEEE Transactions of Nanotechnology 2, 258-264 (2003), which is incorporated herein by reference, the fabrication of SONOS nonvolatile memory devices is described, which comprises a process sequence of a sidewall patterning technique. A layer sequence of silicon, silicon dioxide, and silicon nitride is provided, and the silicon nitride is laterally confined by an etching step. A layer of amorphous silicon is applied conformally all over the surface. An anisotropic etching produces a sidewall spacer adjacent to the silicon nitride layer. The nitride is removed, and the remaining spacer is used as a mask to structure the silicon dioxide layer. The silicon dioxide structure is then used to etch the pattern into the silicon layer. This process sequence is applied to fabricate SONOS memory devices on SOI substrates. A narrow silicon channel with 30 nm width was defined using the sidewall patterning technique. A memory layer sequence of oxide, nitride, and oxide was applied, on which a 100 nm thick polysilicon layer was deposited as gate material. The gate electrode was also patterned by means of the sidewalls patterning technique.
The publication of K. G. Anil et al.: “Layout Density Analysis of FinFETs” in Proceedings of the 33rd European Solid-State Device Research, pp. 139-142, which is incorporated herein by reference, describes FinFETs with either direct patterning or spacer patterning of the active area. The spacer lithography is especially applied to increase the effective device width of the FinFETs. An optimization of the aspect ratio is also discussed.
The publication of M. Specht et al.: “Sub-40 nm tri-gate charge trapping nonvolatile memory cells for high-density applications” in VLSI, 2004 Symposium on VLSI Technology, pp. 244-245, which is incorporated herein by reference, describes tri-gate charge-trapping nonvolatile memory cells in a NAND-type array. The channel region is located on three sides of a silicon fin, which is bridged by a wordline to form the triple gate having a length in the range from 30 nm to 80 nm.